The present invention relates to planarization of semiconductor wafers using a chemical mechanical planarization technique. More particularly, the present invention relates to an improved system and method for planarizing semiconductor wafers in a controlled manner over a variable geometry contact area.
Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor wafer is photolithography. Part of photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive for smaller, more highly integrated circuit designs which cannot tolerate certain nonuniformities within a particular die or between a plurality of dies on a wafer. Because semiconductor circuit on wafers are commonly constructed in layers, where a portion of a circuit is created on a first layer and conductive vias connect it to a portion of the circuit on the next layer, each layer can add or create topography on the wafer that must be smoothed out before generating the next layer. Chemical mechanical planarization (Oxide-CMP) techniques are used to planarize and polish each layer of a wafer. CMP (Metal-CMP) is also widely used to shape within-die metal plugs and wires, removing excess metal from the wafer surface and only leaving metal within the desired plugs and trenches on the wafer. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with a polishing pad rotating in the plane of the wafer surface to be planarized. A chemical polishing agent or slurry containing microabrasives and surface modifying chemicals is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer. Some available wafer polishers use orbital motion, or a linear belt rather than a rotating surface to carry the polishing pad. In all instances, the surface of the wafer is often completely covered by, and in contact with, the polishing pad to simultaneously polish the entire surface. One drawback of polishing the entire surface simultaneously is that the various circuits on the wafer, even if the wafer begins the CMP process perfectly flat, may have a different response to the CMP process. This may be due to the different types of materials deposited on parts of the wafer or the density of materials on a certain portion of the wafer. Simultaneous polishing of the entire surface will often clear some spots of the wafer faster than others because of this differential, uneven rate of clearing and may result in overpolishing of certain areas of the wafer. Various material processes used in formation of wafers provide specific challenges to providing a uniform CMP polish to a wafer. One of the more recent processes used, the copper dual damascene process, can be particularly sensitive to the overpolishing that may occur in polishers that simultaneously polish the entire surface of a wafer. Also, the trends to process larger diameter wafers has introduced an additional level of difficulty to the CMP process by requiring uniformity over a greater surface area.
Accordingly, there is a need for a method and system of performing CMP that addresses these issues.